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Note:
1.
When both /SEL and /RST are active, the MISO output driver is also enabled.
Referring to Figure 6-2 and Figure 6-3 Atmel AT86RF232 MOSI is sampled at the rising
edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal
must be stable before and after the rising edge of SCLK as specified by t 3 and t 4 , refer
to Section 12.4 parameters.
This SPI operational mode is commonly known as “ SPI mode 0 ” .
6.2 SPI Protocol
Each SPI sequence starts with transferring a command byte from the SPI master via
MOSI (see Table 6-2 ) with MSB first. This command byte defines the SPI access mode
and additional mode-dependent information.
Table 6-2 . SPI Command Byte Definition.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access Mode
Access Type
1
1
0
1
Register address [5:0]
Register address [5:0]
Register access
Read access
Write access
0
0
0
0
0
1
0
1
1
1
0
0
reserved
reserved
reserved
reserved
Frame Buffer access
SRAM access
Read access
Write access
Read access
Write access
Each SPI transfer returns bytes back to the SPI master on MISO. The content of the
first byte (see value “ PHY_STATUS “ in Figure 6-4 to Figure 6-14 ) is set to zero after
reset. To transfer status information of the radio transceiver to the microcontroller, the
content of the first byte can be configured with register bits SPI_CMD_MODE
(register 0x04, TRX_CTRL_1). For details, refer to Section 6.3.1 .
In Figure 6-4 to Figure 6-14 and the following chapters logic values stated with XX on
MOSI are ignored by the radio transceiver, but need to have a valid logic level. Return
values on MISO stated as XX shall be ignored by the microcontroller.
The different access modes are described within the following sections.
6.2.1 Register Access Mode
A register access mode is a two-byte read/write operation initiated by /SEL = L. The first
transferred byte on MOSI is the command byte including an identifier bit (bit[7] = 1), a
read/write select bit (bit[6]), and a 6-bit register address.
On read access, the content of the selected register address is returned in the second
byte on MISO (see Figure 6-4 ).
Figure 6-4. Packet Structure - Register Read Access.
byte 1 (command byte)
byte 2 (data byte)
MOSI
MISO
1
0
ADDRESS[5:0]
(1)
PHY_STATUS
XX
READ DATA[7:0]
16
AT86RF232
Note:
1.
Each SPI access can be configured to return radio controller status information
(PHY_STATUS) on MISO, for details refer to Section 6.3 .
8321A – MCU Wireless – 10/11
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